Senior Software Compute Architect (f/m/d)

About us

We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects

About our technology

The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude

In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution

The Role

We are seeking a skilled Senior Software Compute Architect at Black Semiconductor to own the software architecture enabling our next-generation hybrid electronic/photonic compute engine. You will define the programming model, compiler and runtime strategy, and workload-placement mechanisms that allow operations to dynamically execute across the most suitable compute path.

Working closely with the Architecture Lead, Senior Hardware Compute Architect, and software ecosystem teams, you will define how instructions, kernels, and libraries expose the hybrid architecture to higher-level frameworks and enable scalable execution across the platform. Your work will drive performance-focused hardware/software co-design by evaluating AI workloads across candidate architectures and guiding system-level decisions.

This role bridges compiler architecture, heterogeneous compute systems, and electronic-photonic co-design.

To join our team, you should be excited to

• Define the programming model, instruction abstractions, and software interfaces that expose hybrid electronic/photonic compute capabilities to compilers, libraries, and AI frameworks.


• Own the compiler, runtime, and library strategy required to map workloads and kernels to the optimal compute path.


• Develop performance models for AI workloads, including transformer training and inference, to evaluate hardware/software configurations before silicon implementation.


• Partner with the Hardware Compute Architect to co-design interface contracts, telemetry, and control mechanisms enabling dynamic workload movement between compute paths.


• Define software and firmware strategies for scale-up and scale-out execution, including workload distribution and routing across nodes, packages, and systems.


• Prototype kernels, libraries, and runtime concepts to validate architectural decisions against real AI benchmarks.

Your Qualifications

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience.


• 5+ years of experience building compiler, runtime, or systems software for accelerated, heterogeneous, or specialized compute platforms.


• Strong compiler architecture experience, including LLVM, MLIR, or comparable compiler infrastructure targeting custom accelerators or heterogeneous hardware.


• Experience defining instruction sets, programming models, or hardware/software abstractions for novel compute architectures.


• Strong background in kernel and library optimization for AI workloads across different hardware backends.


• Experience modeling AI workload performance, including LLM training and inference, across different hardware architectures.


• Understanding of scale-up and scale-out systems software, including workload distribution, runtime scheduling, and accelerator control-plane interactions.


• Proven ability to collaborate with hardware architects to define shared interfaces and system-level design decisions.


• Experience with compiler, runtime, and AI software ecosystems, including LLVM/MLIR, Triton, CUTLASS-style DSLs, PyTorch, JAX, Python, C++, and profiling/performance-modeling tools for architecture exploration.


• Familiarity with photonic or optical compute concepts and their impact on compiler/runtime strategies will be considered a plus.


• Experience with heterogeneous compute ecosystems such as CUDA, ROCm, Triton, oneAPI, or custom accelerator software stacks will be considered a plus.


• Contributions to open compiler or runtime ecosystems (e.g., MLIR, Triton, PyTorch backends) or exposure to firmware-level scheduling and accelerator control-plane design will be considered a plus.

Our work culture ...